1. Field of the Invention
The present invention generally relates to a solid-state image pickup device and more particularly to a back-illuminated type CMOS (complementary metal-oxide semiconductor) solid-state image pickup device in which incident light is introduced from the back side of a substrate, an electronic apparatus using such solid-state image pickup device and a method of manufacturing such solid-state image pickup device.
2. Description of the Related Art
A CMOS solid-state image pickup device is known as a solid-state image pickup device so far. This CMOS solid-state image pickup device includes a photodiode and a plurality of transistors, that is, MOS (metal-oxide semiconductor) transistors to form one pixel, a plurality of pixels being arrayed with a predetermined pattern. This photodiode is a photo-electric conversion element for generating and accumulating signal electric charges in response to a quantity of light received thereat. The MOS transistors are elements constructing a read circuit to read signal electric charges from the photodiode.
FIG. 1 of the accompanying drawings is a diagram showing an example of a related-art surface-illuminated type CMOS solid-state image pickup device which is applied to an image sensor. FIG. 1 shows a main portion of a pixel. As shown in FIG. 1, a CMOS solid-state image pickup device 1001 includes a first conductivity type, for example, n type silicon substrate 1002 on which a second conductivity type, for example, p type semiconductor well region 1003 is formed, a p type pixel separation region 1004 formed on the surface side of the substrate 1002 to divide each pixel and a unit pixel 1005 composed of a photodiode PD and a plurality of MOS transistors, for example, an electric charge read transistor Tr1, a reset transistor, an amplifier transistor and a vertical selection transistor (all of which are generally denoted by reference numeral Tr2). Many pixels 1005 are arrayed in a two-dimensional fashion.
As shown in FIG. 1, the photodiode PD is formed of a first conductivity type, for example, n type semiconductor region 1006 formed by implanting ions on the surface of the n type semiconductor substrate 1002 by a predetermined depth and a heavily-doped p type semiconductor region formed on the surface of the n type semiconductor region 1006, that is, a p type accumulation layer 1007 to suppress a dark current. The n type semiconductor region 1006 of the photodiode PD is comprised of a heavily-doped n type charge accumulation region (n+ charge accumulation region) 1006a on the surface adjoining to the p+ accumulation layer 1007 and an n type semiconductor region 1006b having an impurity concentration lower than that of the n type charge accumulation region 1006a. 
The above-described respective MOS transistors Tr1 and Tr2 are constructed as follows. That is, a p type semiconductor well region 1009 is formed on the surface of the n type semiconductor substrate 1002 so as to become adjacent to the photodiode PD and heavily-doped n type semiconductor regions, that is, source/drain regions 1010 and 1014 are formed within this p type semiconductor well region 1009 by implanting ions.
The charge read transistor Tr1 is formed of an n+ source/drain region 1010, the n+ charge accumulation region 1006a of the photodiode PD and a gate electrode 1012 formed on the substrate surface between the two regions 1010 and 1006a through a gate insulating film 1011. This n+ source/drain region 1010 becomes a so-called floating diffusion region (FD) and a channel region 1008 is formed right under the gate electrode 1012.
The transistor Tr2 such as a reset transistor, an amplifier transistor and a vertical selection transistor is similarly formed of a pair of n+ source/drain regions 1014 and a gate electrode 1015 formed on the p type semiconductor well region 1009 between the n+ source/drain regions 1014 and 1014 through a gate insulating film, although not shown partly.
Also, a pixel separation region 1019 formed of a p type semiconductor region is formed just under the p type semiconductor well region 1009 corresponding to the read circuit region 1019 on which the two transistors Tr1 and Tr2 of the semiconductor substrate 1002 are formed.
A circuit wiring 1016 of the above-mentioned respective MOS transistors Tr1 and Tr2 is formed of a multilayer wiring through an interlayer insulator 1017. A wiring 1017 is formed only within a read circuit region 1018 and this wiring 1017 is not formed on the photodiode PD because it blocks light introduced from the substrate surface side. Although not shown, a color filter and an on-chip microlens are formed on this multilayer wiring layer through a planarization film.
In this CMOS solid-state image pickup device 1001, light L is introduced from the surface side of the semiconductor substrate 1002 into the photodiode PD, signal electric charges (electrons in this example) e corresponding to an amount of light photo-electrically converted within the photodiode PD are accumulated in the n+ charge accumulation region 1006a and the thus accumulated signal electric charges are read out through the read circuit formed of the respective MOS transistors Tr1 and Tr2.
On the other hand, the assignee of the present application has previously proposed a back-illuminated type CMOS solid-state image pickup device in which light is introduced from the back side of the substrate (see Cited Patent Reference 1). As shown in FIG. 2, a p type pixel separation region 1023 is formed on, for example, an n type silicon semiconductor substrate 1022 and photodiodes PD and a plurality of MOS transistors Tr1 and Tr2 are formed on respective pixel regions to thereby form a unit pixel 1025, a large number of pixels 1025 being arranged in a two-dimensional matrix fashion. The pixel separation region 1023 is formed of, for example, a p type semiconductor region from the surface of the substrate to the back surface of the substrate. The photodiode PD is composed of an n type semiconductor substrate 1022 encircled by the p type pixel separation region and a relatively deep p type semiconductor well region in which each MOS transistor is formed and heavily-doped p type semiconductor regions on the surface and back surface of the substrate, that is, p+ type accumulation layers 1026 and 1027 for suppressing a so-called dark current. The n type semiconductor substrate 1022 of the photodiode PD is composed of a heavily-doped n+ type charge accumulation region 1022a on the substrate surface side and an n type semiconductor region 1022b extended to the back surface side of the substrate and of which impurity concentration is lower than that of the n+ charge accumulation region. The n type semiconductor region 1022b extended to the back surface side of this substrate is formed so as to be extended under a p type semiconductor well region 1024 corresponding to a so-called read circuit region in which each MOS transistor is formed.
A plurality of MOS transistors Tr1 and Tr2 can be formed of four MOS transistors of, for example, a charge read transistor, a reset transistor, an amplifier transistor and a vertical selection transistor similarly as described above. In FIG. 2, the charge read transistor is denoted by reference numeral Tr1 and other reset transistor, amplifier transistor and vertical selection transistor are denoted by reference numerals Tr2. The charge read transistor Tr1 is composed of an n+ source/drain region 1029, an n+ charge accumulation region 1022a of the photodiode PD and a gate electrode 1030 formed on the substrate surface between the two regions 1029 and 1022a through a gate insulating film. This n+ source/drain region 1029 becomes a so-called floating diffusion (FD). A channel region 1034 is formed just under the gate electrode 1030.
The transistor Tr2 such as other reset transistor, amplifier transistor and vertical selection transistor is similarly composed of a pair of source/drain regions 1031 and 1032 and a gate electrode 1033 formed on a p type semiconductor well region 1024 between the source/drain regions 1031 and 1032 through a gate insulating film although not shown partly. Although not shown, a color filter and an on-chip microlens are formed on the back surface side of the substrate through an insulating film which serves as a planarization film as well.
In the back-illuminated type CMOS solid-state image pickup device 1021, light is introduced from the back side of the semiconductor substrate 1022 into the photodiode PD, signal electric charges corresponding to an amount of received light photo-electrically-converted in the photodiode PD are accumulated in the n+ charge accumulation region 1022a and these signal electric charges are read out through the read circuit formed of the respective MOS transistors Tr1 and Tr2.
Also, in recent years, video cameras and electronic cameras are widely used and these cameras use CCD (charge-coupled device) type and amplification type solid-state image pickup devices. Of these solid-state image pickup devices, the amplification type solid-state image pickup device (CMOS image sensor) includes an image pickup pixel unit in which one semiconductor chip has a plurality of pixels arranged thereon in a two-dimensional fashion and a peripheral circuit unit disposed at the outside of the image pickup pixel unit.
Each pixel of the image pickup pixel unit has formed therein an FD (floating diffusion) unit and various kinds of CMOS transistors such as transfer transistors and amplification transistors. Light incident on each pixel is photo-electrically-converted by a photodiode to generate signal electric charges. The signal electric charges are transferred to the FD unit by the transfer transistor and fluctuation of potential at this FD unit is detected by the amplification transistor, the thus detected fluctuation of potential is converted into and amplified to an electric signal and a signal of every pixel is outputted from the signal line to the peripheral circuit unit.
Further, the peripheral circuit unit includes a signal processing circuit for effecting predetermined signal processing, such as CDS (correlation double sampling), gain control and A/D (analog-to-digital) conversion, on a pixel signal from the image pickup pixel unit and a drive control circuit for controlling an output of a pixel signal by driving each pixel of the image pickup pixel unit, such as vertical and horizontal scanners and a timing generator (TG).
In order to produce a small CMOS camera module, there is developed a method of connecting a CMOS solid-state image pickup device and a signal processing device as one chip. To improve sensitivity and shading characteristics, there is developed a so-called back-illuminated type CMOS image sensor having a structure to introduced light from the back surface of the opposite side of the surface in which a read circuit for reading a signal from a photo-electric conversion element is formed.
FIG. 3 is a schematic cross-sectional view showing an arrangement of an image sensor in which the above-described back-illuminated type CMOS solid-state image pickup device is mounted.
As shown in FIG. 3, a sensor chip 101 having an image pickup pixel unit and a signal processing chip 102 having a peripheral circuit unit such as a signal processing circuit are mounted on an interposer (intermediate substrate) 103, for example.
In the sensor chip 101, an interlayer insulator 60 is formed on a supporting substrate 70 and a wiring layer 61 is buried into the interlayer insulator 60. A semiconductor layer 52 is formed above the wiring layer 61 and a surface insulating layer 51 is formed on the surface of the semiconductor layer 52.
A photodiode 54 serving as a photo-electric conversion element and a test electrode 53 and the like are formed in the semiconductor layer 52. Also, a part of the wiring layer 61 serves as a gate electrode formed on the semiconductor layer 52 through a gate insulating film, thereby resulting in a CMOS transistor 55 being constructed.
Further, a semiconductor layer penetrating wiring 56 is formed so as to be connected to the wiring layer 61 through the semiconductor layer 52, a part of the surface insulating film 51 is removed near the portion in which the semiconductor layer penetrating wiring 56 is formed and a pad electrode 57 is formed so as to be connected to the semiconductor layer penetrating wiring 56.
The sensor chip 101 having the above-described arrangement is the so-called back-illuminated type CMOS solid-state image pickup device in which light is irradiated on the photodiode 54 formed in the semiconductor layer 52 from the side of the surface insulating film 51 to generate signal electric charges, the thus generated signal electric charges being accumulated in the photodiode 54. The CMOS transistor 55 has functions to transfer signal electric charges accumulated in the photodiode 54 to the FD unit, to amplify or reset the electric signal.
In the above-described arrangement, the semiconductor layer is obtained by decreasing the thickness of the back surface of the semiconductor substrate and has a structure in which the semiconductor substrate is bonded to the supporting substrate 70 in order to stabilize the shape of the substrate.
The above-described sensor chip 101 is mounted on the interposer 103 in which a wiring 80 and an insulating layer 81 for insulating the wiring 80 are formed on the surface from the side of the supporting substrate 70 of the opposite side of the light illuminated side by a suitable means such as an adhesive layer. The wiring 80 and the pad electrode 57 are electrically connected by wiring bonding 82a. 
On the other hand, the signal processing chip 102 with the peripheral circuit unit formed thereon is mounted on the interposer 103 through bumps, for example, by flip-chip bonding.
The electronic device having the above arrangement is mounted on other mounted substrate at every interposer 103 and these electronic devices are electronically connected by a suitable method such as the wire bonding 82b. 
A method of manufacturing an image sensor in which the above-described related-art back-illuminated type CMOS solid-state image pickup device is mounted on the mounted substrate will be described.
As shown in FIG. 4A, the insulating film 51 made of silicon oxide and which will become a surface insulating film in the later process is formed on the surface of the semiconductor substrate 50 made of silicon and the like, and an SOI (semiconductor on insulator) substrate in which the semiconductor layer 52 made of silicon and the like is formed is formed on the upper layer of the insulating film 51, thereby resulting in the test electrode 53 being formed.
Next, as shown in FIG. 4B, the photodiode 54 is formed in the semiconductor layer 52 by implanting ions of conductive impurities. Further, the gate electrode is formed on the surface of the semiconductor layer 52 through the gate insulating film and the gate electrode is connected to the photodiode 54 and the like to thereby form the CMOS transistor 55. Further, there is formed the interlayer insulator 60 that covers the CMOS transistor. At that time, the wiring layer 61 is formed in the interlayer insulator 60 while it is buried into the interlayer insulator 60 so as to be connected to the transistor, the semiconductor layer 52 and the like.
Next, as shown in FIG. 4C, the supporting substrate 70 is bonded to the upper layer of the interlayer insulator 60.
Next, as shown in FIG. 4D, the semiconductor substrate 50 is removed by polishing the semiconductor substrate 50 from the surface of the opposite side of the side in which the supporting substrate 70 is bonded to the insulating film 51 until the insulating film 51 is exposed. The insulating film 51 exposed on the surface will be referred to as a “surface insulating film”. In the following processes, the upper and lower relationship will be reversed relative to FIG. 4C for convenience sake of sheet of drawing.
Next, as shown in FIG. 4E, the penetrating wiring 56, which is connected through the semiconductor layer 52 to the wiring layer 61 is formed by removing a part of the surface insulating film 51 and the pad electrode 57 is formed so as to be connected to the penetrating wiring 56.
As described above, there is formed the related-art back-illuminated type CMOS solid-state image pickup device (sensor chip) 101.
The above-described back-illuminated type CMOS solid-state image pickup device (sensor chip) 101 is mounted on the interposer 103 from the side of the supporting substrate 70 of the opposite side of the light illuminated side by a suitable means such as the adhesive layer and connected by the wire bonding 82a. 
On the other hand, the signal processing chip 102 in which the peripheral circuit unit is formed is mounted on the interposer 103 through the bumps by flip-chip bonding and the back-illuminated type CMOS solid-state image pickup device (sensor chip) 101 and the signal processing chip 102 are connected through the wiring formed on the interposer 103. In this manner, there can be manufactured the image sensor in which the above-described related-art back-illuminated type CMOS solid-state image pickup device is mounted on the interposer.
In the back-illuminated type CMOS solid-state image pickup device (image sensor) having the above-described arrangement, since the pad electrode, has to be large enough to be connected by wiring bonding, the chip area is increased unavoidably. Also, since the number of electrodes that can be formed within the chip is limited and high-resistance wiring bonding is used, speed at which a signal is transmitted from the sensor chip to the signal processing device is lowered.
On the other hand, there is developed a back-illuminated type CMOS solid-state image pickup device having an arrangement in which an electrode is led out from the surface of the opposite side of the light illuminated surface. In this case, while the light illuminated surface is being directed in the upper direction, this back-illuminated type CMOS solid-state image pickup device is mounted on the mounted substrate from the side of the surface in which the electrode is formed of the opposite surface.
Cited Patent References 1 and 2 had described the back-illuminated type CMOS solid-state image pickup device in which the electrode is formed on the opposite surface of the light illuminated surface.
[Cited Patent Reference 1]: Official Gazette of Japanese laid-open patent application No. 2003-31785
[Cited Patent Reference 2]: Official Gazette of Japanese laid-open patent application No. 2003-273343
In recent years, in the solid-state image pickup device, it is desirable that pixels should be microminiaturized in order to integrate a large number of pixels at high integration degree so as to meet with needs of high resolution. As shown in FIG. 1, in the case of the above-mentioned surface-illuminated type CMOS solid-state image pickup device 1001, since the photodiode PD and a plurality of transistors Tr1 and Tr2 such as the electric charge read transistors are disposed on the same plane in each pixel region, there is a tendency that the area of one pixel 1005 is increased. For this reason, it becomes difficult to make the pixel size become very small. When the pixel size is made very small, since the area of the photodiode PD is reduced, problems arise, in which the saturation electric charge amount (Qs) is lowered and in which sensitivity is lowered.
On the other hand, as shown in FIG. 2, in the above-mentioned back-illuminated type CMOS solid-state image pickup device 1021, since the light L is introduced from the back surface side of the substrate into this CMOS solid-state image pickup device 1021, it is possible to increase the light-receiving area as compared with the surface-illuminated type CMOS solid-state image pickup device and hence sensitivity can be increased. However, as shown in FIG. 2, in this back-illuminated type CMOS solid-state image pickup device 1021, it is desirable that the electric charges e generated in the photo-electric conversion region portion 1022c corresponding to the lower portion (that is, lower portion of the p type semiconductor well region 1024) of the read circuit formed of a plurality of MOS transistors should be efficiently collected to the n+ charge accumulation region 1022a on the surface side of the substrate, thereby suppressing the saturation electric charge amount (Qs) from being lowered.